Teledyne Technologies

  • Senior Logic Design Engineer

    Job Locations US-TX-Round Rock
    Requisition ID
    2018-6240
    Company Name
    Teledyne LeCroy PSG
    Shift
    1st Shift - Day
    Citizenship/Visa Requirement
    US Citizen/Perm Resident/ Other US Person
  • Company Overview

    TeledyneLecroy PSG develops leading edge test and measurement products that engineering teams around the globe use to develop next generation communications, consumer electronics and computer products.

     

     

     

     

     

     

     

     

     

    Position Summary and Responsibilities

    We are looking for a Logic Design Engineer with the right composition of knowledge, experience, spirit and drive, to join a dynamic team that develops leading edge test and measurement products. 

     

    1. Design and test FPGA circuitry for next generation Test and Measurement Tools:
    • Define logic architecture of various blocks of the design
    • Design these blocks using Verilog and verify their block level functionality through simulation
    • Document the design and review with the rest of the team
    • Drive FPGA tools to compile the code and ensure timing closure
    • Verify proper operation of your circuit via system level test with test hardware
    • Work with the verification engineer to validate your circuit in a whole chip simulation environment
    1. Work with customer support to reproduce and fix issues found in the field
    • Reproduce customer environment to reproduce any failures found in the field
    • Fix the RTL, recompile the FPGA and review the changes with the team

     

     

    Qualifications

    • Strong interpersonal, organizational and communication skills– a must!
    • Team Player, Persuasive, encouraging, and motivating
    • Open minded, quick learner, creative, likes challenges Experience at working both independently and in a team-oriented, collaborative environment is essential.
    • Minimum of 5 years of demonstrated experience in FPGA or ASIC design.
    • Ability to effectively prioritize and execute tasks in a high-pressure environment.
    • Knowledge of FPGA tools such as Quartus, Vivado, Modelsim, Signal tap, and Chipscope.
    • Ability to write timing constraints and designs that repeatedly achieve timing closure

     

    • Preferred: 

     

    • Experience with Monitoring and/or Test & Measurement tools. Experience with one or more of the following protocols: PCIe, USB, SAS, SATA, Infiniband
    • Education: BS in EE, CS or Computer Engineering – a must. MS in EE is a plus

     

    Teledyne is an Equal Opportunity/Affirmative Action employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, gender, sexual orientation, gender identity, gender expression, transgender, pregnancy, marital status, national origin, ancestry, citizenship status, age, disability, protected Veteran Status, genetics or any other characteristic protected by applicable federal, state, or local law.    

     

    If you need assistance or an accommodation while seeking employment, please email  teledynerecruitment@teledyne.com or call (805)373-4545.  Determinations on requests for reasonable accommodation will be made on a case-by-case basis.  Please note that only those inquiries concerning a request for reasonable accommodation will receive a response.  

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