Teledyne Technologies Incorporated specializes in providing a broad range of high technology solutions and products to the marketplace. Teledyne Imaging Sensors is an integral member of the new Digital Imaging Segment of Teledyne Technologies. Imaging Sensors provides advanced imaging solutions for a variety of customers, including the DoD, NASA, prime system integrators, and commercial customers. In the civilian space arena, Teledyne sensors are the most advanced sensors on board the Hubble space telescope, and they are also found on board the majority of NASA space probes and ground based telescopes. In the DoD arena, Teledyne sensors are integrated into several major systems for persistent surveillance, chemical detection, and target identification, among others.
Teledyne is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, gender, sexual orientation, gender identity, gender expression, transgender, pregnancy, marital status, national origin, ancestry, citizenship status, age, disability, protected Veteran Status, genetics or any other characteristic protected by applicable federal, state, or local law.
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Essential Duties of the Position:
The senior mixed-signal integrated circuits physical design and tape out engineer will work with other circuit designers to design, physical implementation, develop, modify, and evaluate Read Out Integrated Circuits (ROIC) and their building blocks for various sub-micron technologies. The ability to understand large format ROIC physical design specification and translate them into design solutions for the specific application is an essential quality being sought for this position. The ability to work in a team environment will be a desired characteristic in this position. In this role he/she will also participate in the decision making for the design of individual sub-block, ROIC floor plan, top level integration, and tape out. General duties will include performing block level physical design, top level physical design and implementation, layout parasitic extraction, physical design verification and tape out activities.